|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:40 |
Welcome Remarks |
| 09:40 - 10:40 |
Enabling System Innovation & Guest Speakers |
| 10:40 – 11:00 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Talks |
| 11:00 – 11:30 |
TSMC 3Dblox™: Unleashing The Ultimate 3DIC Design Productivity
TSMC
|
TSMC N3E FinFlex™ Technology: Motivation, Design Challenges, and Solutions
TSMC
|
Analog Migration with Analog Cells
TSMC
|
|
HPC & 3DIC Track |
Mobile & Automotive Track |
IoT, RF & Other Track |
| 11:30 – 12:00 |
Achieve 400W Thermal Envelope for AI-Enabled Data Center SoCs - Challenge Accepted
Alchip / Synopsys
|
Implementation challenges of big CPUs on moving the context from Flat to Hierarchical approach
Arm
|
Establishing the Foundation of Chip Security with Secure OTP for IoT and HPC Applications on TSMC N12e and Advanced Nodes
eMemory
|
| 12:00 – 12:30 |
PCIe 6.0 and CXL 3.0 IP in 5nm for High Performance Computing Applications
Cadence
|
Delivering best TSMC 3nm power and performance with Cadence digital full flow
Cadence
|
Synopsys/Ansys/Keysight mmWave Reference Design Flow on TSMC N16FFC
Synopsys / Ansys / Keysight
|
| 12:30 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 14:00 |
GUC’s 2.5D/3D Chiplets, Interconnect Solutions and Trends
GUC
|
Achieving Best Performance-per-Watt at TSMC’s N2 and N3E FinFlex Technology using Synopsys Fusion Compiler and Synopsys Digital Design Family
Synopsys
|
Addressing Reliability Challenges with Aging-Aware STA for Advanced Nodes
Cadence
|
| 14:00 – 14:30 |
Advanced-Node IC and CoWoS/3DIC Electromagnetic (EM) Co-Simulation using PeakView
Lorentz / Marvell
|
An Accurate and Low-Cost Flow for Aging-Aware Static Timing Analysis
Synopsys / TSMC
|
The design possibilities of digital PLL on TSMC advanced process
M31 Technology
|
| 14:30 – 15:00 |
HPC & Networking Trends Influencing High-Speed SerDes Requirements
Synopsys
|
Achieving best power and performance for Arm Cortex-X CPUs on TSMC advanced nodes with Cadence digital full flow
Cadence
|
Analysis of Design Timing Effects of Threshold Voltage Mistracking between Cells
Synopsys
|
| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 16:00 |
TSMC 3DBlox Simplifies Calibre Verification and Analysis
Siemens EDA
|
Self-testing PLLs for advanced SoCs
Silicon Creations
|
Cadence Cerebrus AI driven design optimization pushes PPA on TSMC 3nm node
Cadence
|
| 16:00 – 16:30 |
GUC’s GLink case study: Performance and reliability monitoring for heterogeneous packaging, combining deep data with machine learning algorithms
proteanTecs
|
Analog Design Migration Flow from TSMC N5/N4 to N3E with Synopsys Case Study
Synopsys
|
Integration Methodology of High-End SerDes IP into FPGAs based on Early Technology Model Availability
Achronix / Alphawave IP
|
| 16:30 – 17:00 |
Simultaneous multi-corner extraction for 3DICs
Synopsys
|
Kick-off your design success with Automated Migration of Virtuoso Schematics
Cadence
|
Effective Hierarchical Thermal Analysis Solution with ML-enabled technology for 3DIC system
Ansys
|
| 17:00 – 18:00 |
Networking and Reception |
