Agenda：Online Event (North America)

Exhibit Now!

Join the Ecosystem Pavilion and reach approximately 1,000 director level and above executives from our customers!!

Register Now

Date: Thursday, November 10, 2022

Plenary Session
Welcome & Ecosystem Pavilion
Opening Remarks
Enabling System Innovation & Guest Speaker

Included All In-Person Papers

HPC & 3DIC Track

Advanced-Node IC and CoWoS/3DIC Electromagnetic (EM) Co-Simulation using PeakView

Lorentz / Marvell

Design Stage Thermal Gradient Based Static Timing Analysis

Synopsys

How to Fix IR-drop Without Hurting Timing: A Joint Ansys-Synopsys IR-ECO Signoff Flow

Ansys

GDDR6 Memory Interface Solution for High-Performance AI/ML Inference Accelerators

Rambus

Effective Hierarchical Thermal Analysis Solution with ML-enabled technology for 3DIC system

Ansys

Accelerate DRC Convergence by Scaling IC Validator Signoff on Cloud

Synopsys / Microsoft

AWS case study: Reducing carbon emissions in the semiconductor value chain

AWS

Evolutionary to Revolutionary: Moving to 8533+ MT/s operation for LPDDR5/5X designs at TSMC N5 and N4P

Cadence

Securing System-in-Packages with PUF Technology

Intrinsic ID

RISC-V Evolves into Mainstream of Computing Using TSMC's Latest Process Technology

Andes

TSMC DRC Sign-Off in the Cloud with Pegasus™

Cadence
Mobile & Automotive Track

Implementation challenges of big CPUs on moving the context from Flat to Hierarchical approach

Arm

Use of High-Performance Analog Signal Chains to Enable Automotive and 5G Applications

Omni Design Technologies

Addressing Reliability Challenges with Aging-Aware STA for Advanced Nodes

Cadence / TSMC

Exploring World of AI-Driven Physical Design Applications on TSMC advanced process nodes

Synopsys

Pushing performance on the latest generation Arm Cortex-X CPU at TSMC N4P technology

Arm
IoT, RF & Other Track

Electromagnetic modeling of advanced process features and layout dependent effects using Ansys RaptorX

Ansys

Layered electromagnetic extraction and EMIR analysis with passive devices

Cadence

Securing the AI product lifecycle: RapidSilicon’s use of PUFcc for OpenFPGA on TSMC 16nm

eMemory

Establishing the Foundation of Chip Security with Secure OTP for IoT and HPC Applications on TSMC N12e and Advanced Nodes

eMemory

*The agenda is subject to change by TSMC.

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.