Agenda：Online Event

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Join the TSMC OIP Ecosystem Forum and get first-hand updates on TSMC's advanced and specialty technologies, advanced backend capabilities and future development plans!

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Date: Tuesday, December 13, 2022

Plenary Session
Welcome & Ecosystem Pavilion
Opening Remarks
Enabling System Innovation
TSMC Technical Talks

TSMC 3Dblox™: Unleashing The Ultimate 3DIC Design Productivity

TSMC

Analog Migration with Analog Cells

TSMC
HPC & 3DIC Track

Achieve 400W Thermal Envelope for AI-Enabled Data Center SoCs - Challenge Accepted

Alchip / Synopsys

GUC’s 2.5D/3D Chiplets, Interconnect Solutions and Trends

GUC

Novel CPM for High Performance GPU Chip-Package-System Power Integrity Analysis

Moore Threads / Ansys

Simplifying Multi-chiplet design with a unified 3D-IC platform solution for 3Dblox technology

Cadence

A novel practical and accurate system power integrity analysis methodology for GPGPU

Iluvatar CoreX

A High-Fidelity Voltage-Aware-Timing Signoff Solution in Advance Technology

Sanechips / Ansys

TSMC 3DBlox Simplifies Calibre Verification and Analysis

Siemens EDA

HPC & Networking Trends Influencing High-Speed SerDes Requirements

Synopsys

A systematic solution for a faster silicon interposer design and its PI & SI challenges

MetaX Integrated Circuits

GUC’s GLink case study: Performance and reliability monitoring for heterogeneous packaging, combining deep data with machine learning algorithms

proteanTecs

Understanding UCIe for Multi-Die SoCs Leveraging CoWoS and Substrate Packaging Technologies

Synopsys

How to Fix IR-drop Without Hurting Timing: A Joint Ansys-Synopsys IR-ECO Signoff Flow

Ansys

Accurate 3DIC thermal simulation for BEOL influence study

ZTE

High performance TIM1 for CoWoS Package

Sanechips
Mobile, IoT & Automotive Track

Achieving best power and performance for Arm Cortex-X CPUs on TSMC advanced nodes with Cadence digital full flow

Cadence

Delivering best TSMC 3nm power and performance with Cadence digital full flow

Cadence

An Accurate and Low-Cost Flow for Aging-Aware Static Timing Analysis

Synopsys / TSMC

Advanced DFR&DFM solutions for balancing reliability and PPAC

Sanechips / ZTE

Achieving Best Performance-per-Watt at TSMC’s N3E Process Technology Nodes using Fusion Compiler and the Fusion Design Family

Synopsys

Implementation challenges of big CPUs on moving the context from Flat to Hierarchical approach

Arm

A Comprehensive Electromagnetic Analysis Flow for Transmission Line in High-Speed AMS Design

Sanechips / Ansys

Achievement of ASIL-D Level of Functional Safety in SiEngine’s 7nm Automotive Infotainment SoC Leveraging Unified FuSa Verification Solution

SiEngine Technology

Using Quantus FS for silicon-precision extraction for advanced node SRAM and Standard Cells designs

Cadence

Synopsys / Ansys / Keysight mmWave Reference Design Flow on TSMC N16FFC

Synopsys / Ansys / Keysight

Analog Design Migration Flow from TSMC N5/N4 to N3E with Synopsys Case Study

Synopsys

Cadence mmWave Solutions Support TSMC N16 Design Reference Flow

Cadence

Self-testing PLLs for advanced SoCs

Silicon Creations

Establishing the Foundation of Chip Security with Secure OTP for IoT and HPC Applications on TSMC N12e and Advanced Nodes

eMemory

Kick-off your design success with Automated Migration of Virtuoso Schematics

Cadence

*The agenda is subject to change by TSMC.

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.