|
Time
|
Plenary Session
|
| 08:00 - 09:00 |
Registration & Ecosystem Pavilion |
| 09:00 - 09:15 |
Welcome Remarks |
| 09:15 - 10:10 |
Enabling System Innovation & Guest Speaker
|
| 10:10 – 10:30 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Talks |
| 10:30 – 11:00 |
TSMC 3Dblox™: Unleashing The Ultimate 3DIC Design Productivity
TSMC |
TSMC N3E FinFlex™ Technology: Motivation, Design Challenges, and Solutions
TSMC |
Analog Migration with Analog Cells
TSMC |
|
HPC & 3DIC Track |
Mobile & Automotive Track |
IoT, RF & Other Track |
| 11:00 – 11:30 |
GUC’s 2.5D/3D Chiplets, Interconnect Solutions and Trends
GUC |
Analog Design Optimization by Integrating MediaTek’s ML-based Engine within the Virtuoso’s Analog Design Environment
MediaTek / Cadence |
Synopsys / Ansys / Keysight mmWave Reference Design Flow on TSMC N16FFC
Synopsys / Ansys / Keysight |
| 11:30 – 12:00 |
A Unified Approach to 3DIC Power and Thermal Integrity Analysis Through TSMC 3Dblox Architecture and Ansys RedHawk-SC Platform
Ansys |
Achieving Best Performance-per-Watt at TSMC’s N2 and N3E FinFlex Technology using Synopsys Fusion Compiler and Synopsys Digital Design Family
Synopsys |
Breakthrough platform for AIoT markets
Dolphin Design |
| 12:00 – 13:00 |
Lunch & Ecosystem Pavilion |
| 13:00 – 13:30 |
SerDes clocking catered to robust noise handling in advanced process technologies for HPC, Datacenter, 5G and AI applications
eTopus Technologies / Siemens EDA |
An Accurate and Low-Cost Flow for Aging-Aware Static Timing Analysis
Synopsys / TSMC |
Cadence mmWave Solutions Support TSMC N16 Design Reference Flow
Cadence |
| 13:30 – 14:00 |
Advanced Assembly Verification for TSMC 3DFabric™ Packages
Broadcom / Siemens EDA |
Analog Design Migration Flow from TSMC N5/N4 to N3E with Synopsys Case Study
Synopsys |
Analysis of Design Timing Effects of Threshold Voltage Mistracking between Cells
Synopsys |
| 14:00 – 14:30 |
Simplifying Multi-chiplet design with a unified 3D-IC platform solution for 3Dblox technology
Cadence |
Low power high density design implementation for AI chip
Hailo Technologies / Siemens EDA |
RISC-V is delivering performance and power efficiency from Embedded to Automotive to HPC
SiFive / Synopsys |
| 14:30 – 15:00 |
Advanced Auto-Routing for TSMC® InFO™ Technologies
Cadence |
Reliable compute – taming the soft errors
Arm |
TSMC, Microsoft Azure and Siemens EDA Collaboration - Enabling Your Jump to N3E using the Cloud and Calibre nmDRC
Siemens EDA / Microsoft |
| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 16:00 |
3D System Integration and Advanced Packaging for next-generation multi-die system design using Synopsys 3DIC Compiler with TSMC 3DBlox and 3DFabric
Synopsys |
Self-testing PLLs for advanced SoCs
Silicon Creations |
HPC & Networking Trends Influencing High-Speed SerDes Requirements
Synopsys |
| 16:00 – 16:30 |
TSMC 3DBlox Simplifies Calibre Verification and Analysis
Siemens EDA |
Cadence Cerebrus AI driven design optimization pushes PPA on TSMC 3nm node
Cadence |
Integration Methodology of High-End SerDes IP into FPGAs based on Early Technology Model Availability
Achronix / Alphawave IP |
| 16:30 – 17:00 |
GUC’s GLink case study: Performance and reliability monitoring for heterogeneous packaging, combining deep data with machine learning algorithms
proteanTecs |
Kick-off your design success with Automated Migration of Virtuoso Schematics
Cadence |
Pinless Clocking and Sensing
Analog Bits |
| 17:00 – 17:30 |
Achieve 400W Thermal Envelope for AI-Enabled Data Center SoCs - Challenge Accepted
Alchip / Synopsys |
Delivering best TSMC 3nm power and performance with Cadence digital full flow
Cadence |
Understanding UCIe for Multi-Die Systems Leveraging CoWoS and Substrate Packaging Technologies
Synopsys |
| 17:30 – 18:30 |
Networking and Reception
|
