Agenda：Online Event

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Join the TSMC OIP Ecosystem Forum and get first-hand updates on TSMC's advanced and specialty technologies, advanced backend capabilities and future development plans!

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Date: Monday, November 25, 2024

Plenary Session
Welcome & Ecosystem Pavilion
Opening Remarks
TSMC Keynote & Guest Speech

Included All In-Person Papers

HPC & 3DFabric Track

HBM3/HBM3E Implementation Challenges When Integrating Memory Controllers with Physical Layer Solutions, and How to Overcome them

Rambus / Cadence

Addressing 3DIC Design Reliability Challenges with a Cutting-Edge Mechanical Stress Modeling and Simulation Approach

Cadence

Leveraging TSMC’s CoWoS Interposer and Synopsys’ SLM IP to Monitor, Test, and Repair Multi-Die Designs

Synopsys / TSMC

A Unified AI-Driven Platform for Multi-Die Exploration and Design

Synopsys

High-Speed Interface IP Scaling to Meet Data Center AI Demands

Synopsys

Total solution for high-speed data transfers with M31's ONFI-V6.0 Multi-PHY in TSMC N3P

M31 Technology

A High-Performance Silicon Lifecycle Management Architecture for 3D and Multi-Die Systems

Siemens EDA

Enabling Tomorrow’s AI/ML Workloads with Standards-Based Protocol IP in Advanced Technology Processes

Cadence

Design of vertical fiber-to-chip coupling system in TSMC’s COUPE Silicon Photonics platform for Co-Packaged Optics and In-Package Optical I/O applications

Ansys

Enabling a Battery-Free IoT Future: Sofics and ONiO Collaboration on Ultra-Low Leakage ESD Protection

Sofics / ONiO
Mobile, IoT & Automotive Track

AWS cloud technologies improves productivity for Calibre® PERC™ reliability verification workloads

Siemens / Amazon Web Services

Chip Design - Cloud and Efficiency

Google

Leveraging AI/ML as the next leap to custom design automation

Cadence / Renesas

Leveraging AI to correctly identify critical corners for statistical .lib characterization on automotive cell libraries

Siemens EDA / Infineon Technologies

Workload-Aware Dynamic Power Reduction with a Reliability Protection-Layer

proteanTecs

AI-based RF design synthesis flow

Synopsys

High Performance SiFive RISC-V N3E Cores enablement using Synopsys QIK flow

Synopsys / SiFive

AI-Driven Analog Design Migration Solution Tuned for TSMC Technology Platforms

Synopsys

The low voltage USB4 PHY for Type-C applications

M31 Technology

*The agenda is subject to change by TSMC.

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.