|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:45 |
Welcome Remarks |
| 09:45 - 10:30 |
Keynote Session by TSMC and Google |
| 10:30 – 11:00 |
Coffee Break & Ecosystem Pavilion |
|
TSMC Technical Talks |
| 11:00 – 11:30 |
3Dblox 2024: Maximize 3DIC Design Productivity
TSMC
|
Energy efficient N2P and A16 SPR Technology Enablement
TSMC
|
AI-powered EDA Solutions for Design PPA, QoR and Productivity Enhancement
TSMC
|
|
OIP Partner Technical Talks |
|
3DFabric & 3Dblox Track |
HPC & Mobile Track |
Automotive, IoT & RF Track |
| 11:30 – 11:50 |
Routing of Multi-Chiplet TSMC 3DFabric technologies
Cadence
/ AMD
|
Chiplets and the Arm Chiplet System Architecture
Arm
|
Groundbreaking SRAM Repair Toolset: Pre-integrated Siemens Tessent MBIST with eMemory’s NeoFuse OTP
eMemory
/ Siemens EDA
|
| 11:50 – 12:10 |
Architecting next generations Terabit AI networks with Industry’s First Multi-Protocol I/O Connectivity Chiplet
Alphawave Semi
/ Arm
|
Broadcom deliver TSMC N3 high performance designs with Cadence AI driven digital full flow
Cadence
/ Broadcom
|
Developing Next-Gen Battery Charging Technology Partnering with TSMC and Synopsys for a Sustainable Energy Future
Synopsys
/ Iontra
|
| 12:10 – 12:30 |
Effective methods to reuse and automate bump creation for chiplets in 3DIC designs
Synopsys
/ AMD
|
Thermal modeling of backside power delivery structure –- a N2 process case practice
Ansys
|
Leveraging AI/ML as the next leap to custom design automation
Cadence
/ Renesas
|
| 12:30 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 13:50 |
3DIC Physical Implementation and SoIC-X Silicon Testing Results
GUC
|
Utilizing an AI-powered methodology to achieve SPICE-accurate 7-sigma statistical yield verification
Siemens EDA
|
A comprehensive IP validation methodology for Microsoft’s AI and high-performance compute chips
Siemens EDA
/ Microsoft
|
| 13:50 – 14:10 |
Hierarchical flow innovation for Large Silicon Interposer (3X reticle size CoWoS-S) designs for faster turnaround and productivity improvement
Cadence
/ Broadcom
|
EDA Flow Cloud Certification – a collaboration between TSMC, AWS and Siemens EDA
Siemens EDA
/ AWS / TSMC
|
A Unified AI-Driven Platform for Multi-Die Exploration and Design
Synopsys
|
| 14:10 – 14:30 |
A Collaborative Study on 2.5D System in Package for Better Quality and Reliability of High Bandwidth Memory
SK hynix
|
Design of vertical fiber-to-chip coupling system in TSMC’s COUPE Silicon Photonics platform for Co-Packaged Optics and In-Package Optical I/O applications
Ansys
|
New approach that targets EM/IR hotspot analysis and fixing with mPower and Calibre DesignEnhancer
Siemens EDA
|
| 14:30 – 14:50 |
Efficient 3D Chiplet Stacking Using TSMC SoIC Technology
Alchip
/ Synopsys
|
Realizing benefits of Backside Power and Clock on TSMC A16 technology node
Synopsys
|
Enabling a Battery-Free IoT Future: Sofics and ONiO Collaboration on Ultra-Low Leakage ESD Protection
Sofics
/ ONiO
|
| 14:50 – 15:10 |
Ansys-Synopsys-TSMC Solve the 3DIC Multiphysics Challenges
Synopsys
/ Ansys
|
Advanced Verification of Microsoft MAIA AI Processor 3DIC
Siemens EDA
/ Microsoft
|
Accelerating the Verification of High-Frequency Mixed-Signal Components via Jivaro Pro Advanced Parasitic Reduction
Silvaco
/ Silicon Creations
|
| 15:10 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 15:50 |
Simplifying requirements and flows of SoIC technology for Stacked die design with TSMC 3Dblox and Cadence Integrity 3D-IC Platform
Cadence
/ GUC
|
Secure remote debug with Siemens Calibre in Azure Modeling and Simulation Workbench
Microsoft
/ Siemens EDA
|
GDDR Memory for High-Performance AI Inference
Cadence
/ Rambus
|
| 15:50 – 16:10 |
HBM3/HBM3E Implementation Challenges When Integrating Memory Controllers with Physical Layer Solutions, and How to Overcome them
Rambus
/ Cadence
|
Mastering the Timing Closure Maze for Enhanced Productivity and Efficiency
Cadence
/ Intel
|
Revolutionizing RC Parasitic Extraction: The Power of StarRC Hybrid Extraction
Synopsys
/ TSMC
|
| 16:10 – 16:30 |
Multi-die design for TSMC COUPE with unified electronic and photonic design solutions
Synopsys
/ Ansys
|
Leveraging AI to accelerate debug with Calibre Design Solutions
Siemens EDA
|
Chip Design - Cloud and Efficiency
Google
|
| 16:30 – 16:50 |
The Future of Hardware Technologies for Computing
Stanford University
|
The Future of Hardware Technologies for Computing
Stanford University
|
The Future of Hardware Technologies for Computing
Stanford University
|
| 16:50 – 18:00 |
Networking and Reception |
