Agenda：Online Event

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Join the TSMC OIP Ecosystem Forum and get first-hand updates on TSMC's advanced and specialty technologies, advanced backend capabilities and future development plans!

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Date: Monday, November 25, 2024

Plenary Session
Welcome & Ecosystem Pavilion
Opening Remarks
TSMC Keynote

Included All In-Person Papers

HPC & 3DFabric Track

Simplifying requirements and flows of SoIC technology for Stacked die design with TSMC 3Dblox and Cadence Integrity 3D-IC Platform

Cadence / GUC

Die-to-Die Physical-Aware Interconnect Testing Using 3Dblox For Reduced Manufacturing Test Cost

Siemens EDA / TSMC

Design of vertical fiber-to-chip coupling system in TSMC’s COUPE Silicon Photonics platform for Co-Packaged Optics and In-Package Optical I/O applications

Ansys

Distributed and GPU-accelerated 3D EM Simulations for IC and 3DIC Silicon Photonics Applications with Peakview

Lorentz Solution / NVIDIA

Leveraging TSMC’s CoWoS Interposer and Synopsys’ SLM IP to Monitor, Test, and Repair Multi-Die Designs

Synopsys / TSMC

HBM3/HBM3E Implementation Challenges When Integrating Memory Controllers with Physical Layer Solutions, and How to Overcome them

Rambus / Cadence

PCIe gen 7 and 48Gbps UCIe at N6

eTopus

Developing Next-Gen Battery Charging Technology Partnering with TSMC and Synopsys for a Sustainable Energy Future

Synopsys / Iontra

AI Driven Layout Optimization For T-Coil Matching Networks

Ansys / AMD

AI-Driven Analog Design Migration Solution Tuned for TSMC Technology Platforms

Synopsys
Mobile, IoT & Automotive Track

Revolutionizing RC Parasitic Extraction: The Power of StarRC Hybrid Extraction

Synopsys / TSMC

Leveraging AI to correctly identify critical corners for statistical .lib characterization on automotive cell libraries

Siemens EDA / Infineon Technologies

Fast Vt skew analysis for highly accurate global variation modeling

Synopsys / TSMC

A library-focused approach to standard cell IP evaluation and selection for automotive ICs

Siemens EDA / Infineon Technologies

Low-Power Communication IC Design Verified by AI-Powered Simulation Flow

Siemens EDA / THine Electronics

Groundbreaking SRAM Repair Toolset: Pre-integrated Siemens Tessent MBIST with eMemory’s NeoFuse OTP

eMemory / Siemens EDA

Leveraging AI/ML as the next leap to custom design automation

Cadence / Renesas

Mastering the Timing Closure Maze for Enhanced Productivity and Efficiency

Cadence / Intel

Using Quantus Insight for Intelligent Debugging, Optimization, and Signoff Closure

Cadence / CelestialAI

*The agenda is subject to change by TSMC.

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.