|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:45 |
Welcome Remarks |
| 09:45 - 10:30 |
TSMC Keynote & Guest Speech |
| 10:30 – 11:00 |
Coffee Break & Ecosystem Pavilion |
| 11:00 – 11:30 |
TSMC 3Dblox & 3DFabric Flow
TSMC
|
TSMC Analog Migration
TSMC
|
|
HPC & 3DIC Track |
Mobile, IoT & Automotive Track |
| 11:30 – 12:00 |
GUC’s Chiplet Solutions from 2.5D to 3D
GUC
|
Synopsys/Ansys/Keysight RF Reference Design Flow on TSMC Advanced N4P Process
Synopsys
/ Keysight / Ansys
|
| 12:00 - 12:30 |
A Case Study Demonstrating the Advantages of 224G Interconnects and 3DIC Architectures for Artificial Intelligence ICs
Alchip
/ Synopsys
|
Custom Design Migration in Virtuoso Studio: A comprehensive solution for migration across nodes
Cadence
|
| 12:30 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 14:00 |
Cisco Characterization using PrimeLib on Synopsys Cloud for TSMC Advanced Node Libraries
Synopsys
/ Cisco
|
Achieving TSMC N3 and N2 design goals using Cadence Cerebrus AI enabled digital full flow
Cadence
|
| 14:00 – 14:30 |
Real Examples of 3D Heterogeneous Integration Using the TSMC 3Dblox Standard
Synopsys
|
Attacking resistance, the key limiter in achieving EMIR clean results, with layout modifications
Siemens EDA
/ MediaTek
|
| 14:30 – 15:00 |
Using 3Dblox to simplify and automate 3DFabric design
Cadence
|
Optimizing compute density for SiFive RISC-V processors in TSMC advanced nodes with Synopsys Fusion QuickStart Implementation Kits
Synopsys
/ SiFive
|
| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 16:00 |
Demonstrating Technology PPA Entitlement with TSMC’s N2 Technology on HPC Design Using Synopsys Fusion Compiler
Synopsys
|
Addressing reliability challenges with aging-aware STA for advanced nodes
Cadence
/ nVidia
|
| 16:00 – 16:30 |
The Rise of Chiplets in Advanced AI / ML / High Performance Compute SoC's
Credo Semiconductor
|
The SoC Anchor in Advanced Technology: An One-stop-shop NeoFuse NVM Solution
eMemory Technology Inc.
|
| 16:30 – 17:00 |
The Next Wave: 224G Serial Link
Cadence
|
Synopsys AI-based Analog Design Migration Flow for TSMC Advanced Technologies
Synopsys
|
| 17:00 – 17:30 |
Leveraging UCIe for High-Speed Stack Testing of Multi-Die Systems through Monitoring, Test & Repair (MTR) and HSAT IPs
Synopsys
/ TSMC
|
The latest generation of USB4 PHY for Type-C Application.
M31 Technology
|
| 17:30 - 17:45 |
Lucky Draw |
