HPC & 3DFabric Track   

Ensuring Reliability and Interoperability Using UCIe IP and CoWoS Technology

The drive to multi-die systems is well underway, bringing keystone companies in the semiconductor ecosystem closer together to move the industry forward. Such ecosystem collaborations are resulting in essential technologies and solutions that companies need to overcome their challenges and innovate products we can’t live without.

Synopsys and TSMC are among the keystone companies that are closely collaborating to deliver solutions for fast heterogeneous integration. One result is the Synopsys UCIe IP for TSMC’s advanced process nodes and packaging technologies such as InFO and CoWoS. The IP has been tape-out in TSMC’s N5 and N3 processes, supports several protocols including PCIe and CXL, and allows low latency and secure interfaces between dies on the same or different nodes.

This presentation highlights how designers can ensure their multi-die system reliability with Synopsys UCIe IP on TSMC processes. The test, repair and monitoring features can reduce test time and optimize in-field health monitoring. The presentation also highlights the implementation of our UCIe IP testchip on TSMC’s N5 process, focusing on the co-design and validation methodology used for TSMC’s CoWoS interposer.

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