TSMC OIP - Session Information

HPC & 3DFabric Track

Full Path Die-to-die ESD Interconnect Compliance Check in IC Validator PERC

Synopsys

Abstract
Electrostatic Discharge (ESD) compliant interconnects are critical requirements defined in TSMC ESD checker for in-die ESD design verification of traditional single chip packaging. Nowadays, advanced 2.5D/3DIC packaging are on-demand technology to efficiently pack multiple dies onto PCB. With 2.5D/3DIC packaging, ESD paths are naturally extended into interposer/RDL area, and certain ESD interconnect compliance rule requirements, usually measured by P2P effective resistance (P2PR) and current density, are to be checked on a full path base linking die1-to-interposer-to-die2 with micro hybrid bump and C4 bumps are taking into consideration. Full path P2PR and current density measurements involving P/G nets are already challenging for performance of single die run. If trying to stitch two dies and interposer areas to form single piece of GDS data and apply same P2PR/CD measurement flows, it is not an efficient approach at all due to even much larger polygon data to be processed through each step in P2PR or CD flow, both run performance and hardware resource are very challenging to meet. In this presentation, we demonstrate a methodology that stitches resistor networks from multiple dies and interposer areas to measure full path P2PR/CD primarily in matrix solving stage. This methodology avoids handling extreme huge/combined polygon database on layout netlist extractor / netlist analyzer / prune / StarRC steps of P2P/CD flow, and primarily requires matrix solver to take on the job to handle combined resistor networks from multiple dies and interposer areas for full path application. Our case demonstrates production feasibility of full path P2P/CD checks across multiple dies in 2.5D/3DIC packaging.

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