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| Mobile & Automotive Track |
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Enabling SoC level Full Path Current Density checks for ESD compliance
Synopsys
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Abstract
Due to ever shrinking layout geometries and reduction in breakdown voltages of transistors, on-chip ESD protection and ESD interconnect routes play an important role during advanced node (7nm and below) IC design. ESD-compliance is rapidly becoming sign-off critical for most ICs today. ESD events are charge-driven, that involve the rapid flow of accumulated charge (external or internal to the IC) via on-chip interconnects and ESD protection circuitry, to protect the functional circuitry. TSMC’s advanced node PDKs provide a comprehensive array of rule-based checks to ensure ESD-ready sign-off. These checks are recommended to be performed as part of the Physical Verification (PV) cycle in the IC design flow. One of the main pillars of rule-based ESD-checking is current density (CD) checking, to ensure interconnect routes are wide enough to allow safe passage of the ESD currents in a very short time without causing any burn-out of the metal. CD is recommended to be done on all signal nets, and particularly on all supplies, including core supplies. This is also called “Full Path CD Checking” in the TSMC PDK. The core methodology behind this is to perform transistor level Resistance-only (R-only) parasitic extraction (PEX) on ESD-susceptible nets (signals and supplies) in the design, and then run a static operating point simulation on the parasitic network. As the chip gets integrated all the way to its highest level, the data volume continues to grow, making CD checking at top level a challenge for EDA tools. While this is an important check to be done, most SoCs are unable to finish it due to the prolonged runtimes (several weeks), making it impractical during last-mile design closure schedules. Customers with large, nearly reticle-limit sized designs are gated by EDA tool capacity for Full Path CD checking at the SoC level. In this presentation, we will highlight a methodology for successful CD analysis at the SoC level, bringing EDA tool runtimes from several weeks to less than one week. IC Validator PERC is the PV tool for performing CD checks and the StarRC tool is used for embedded parasitic extraction. The designs-under-test (DUT) are all partner customer designs on the TSMC 5nm node. A brief overview of the ESD-checking flow by TSMC will be provided, followed by results of the work done. |
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