IoT, RF & Other Track   17:00 – 17:30

Virtual cross-die Coupling Capacitance Extraction Using Synopsys StarRC

Three-dimensional integrated circuits (3DICs) have been proven as a more efficient solution due to their advantages of higher performance, increasing power density, and optimized power consumption. As a merging technology in the real world, 3DICs make significant achievements in promoting the entire semiconductor industry.

At the leading-edge nodes, accurate parasitic extraction on complicated 3DIC designs has become a new challenge to the whole industry. As the leader in the EDA’s interconnect extraction field, Synposys StarRC provides a complete solution flow to not only handle comprehensive RC extraction on a single die but also consider the cross-die capacitive coupling between two stacking dies. Especially, Synopsys StarRC proposed the virtual interface block (VIB) method to model the cross-die coupling capacitance. An interface block is created from the both stacking dies, and then a full parasitic extraction would be conducted on this block to model the cross-die coupling.

Today’s cross-die parasitic extraction is based on specific physical die-to-die interface. Designers still need at least two dies ready if they would like to verify the cross-die coupling of their 3DIC design. To improve design verification cycles for our collaborators, StarRC offers virtual die solution to estimate the cross-die coupling capacitance. By measuring the parasitic with the virtual metal fill polygons and the mirrored bump shapes from working chiplet, our users can model the cross-die effect in the early production stage. This enhancement can significantly simplify their efforts on designs and verifications. Due to the seamless integration between products from Synopsys, StarRC allows users to do timing analysis for virtual die result. In this presentation, we will cover the advantages of the new enhancement and how it helped to simplify users’ design flow.

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