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| Mobile & Automotive Track 14:30 – 15:00 |
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Optimizing compute density for SiFive RISC-V processors in TSMC advanced nodes with Synopsys Fusion QuickStart Implementation Kits
Synopsys / SiFive
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Abstract
As SiFive’s RISC-V processors continue to increase in performance, complexity, and compute density, users require implementation guidance to achieve optimized performance, power and area (PPA). SiFive’s processor IP portfolio includes the high performance 64-bit RISC-V application processors (the SiFive Performance™ family), the scalable AI processors (the SiFive Intelligence™ family), and 32/64-bit embedded processors (the SiFive Essential™ family). The currently available processors of the Performance family are P450, P470, P650, P670, and P870. With industry-leading compute density (compute per mW, compute per area) and are aimed towards consumer, wearable, home, and mobile markets.
Synopsys has been collaborating with SiFive to develop and deliver Fusion QuickStart Implementation Kits (QIKs) on advanced TSMC nodes like N7, N5, and N3E. They provide a fully-worked RTL-to-GDSII sign-off flow example for these market-leading RISC-V cores. These QIKs are available free through Synopsys’ SolvNetPlus. In this presentation, we will share the results, the challenges that the joint team faced and the solutions they developed that are captured in the QIKs. Additionally, we will also share the ongoing work to develop the next generation SiFive Performance processors in TSMC N3 node. |
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Legal Notice
TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC. |
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