IoT, RF & Other Track   16:30 – 17:00

Leveraging UCIe for High-Speed Stack Testing of Multi-Die Systems through Monitoring, Test & Repair (MTR) and HSAT IPs

Synopsys / TSMC
This joint presentation by Synopsys and TSMC highlights the early collaboration results of a multi-die system demonstrating two configurations: in the first the two dies communicating via high speed UCIe-based die-to-die interface and in the second via standard GPIO-based multi die interface. In the first configuration, the Synopsys Monitoring, Test & Repair (MTR) IP provides interconnect reliability, test & repair feature between two UCIe interface IPs and in the second configuration supports the IEEE 1838 test access infrastructure allowing intra-die lane testing. Both configurations also support full execution of test, monitor, debug, and repair capabilities internal to each die, utilizing on-chip resources such as, Synopsys HSAT and SEQ IPs for random logic blocks, SMS IP for embedded memory blocks; and SHS and MTR IP for UCIe blocks. This presentation will demonstrate how such capabilities can be used throughout the entire lifecycle of the multi-die system. This includes pre-bond and post-bond manufacturing stages, in-field power-on stage, and periodic mission health monitoring stage. The multi-die system leverages TSMC’s CoWoS interposer technology to help demonstrate the above capabilities. Find out more about these new essential features for realizing multi-die systems leveraging Synopsys Silicon Lifecycle Management (SLM) solutions and TSMC’s advanced packaging technology.

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