HPC & 3DFabric Track   

Enabling the transition to terabit-scale Ethernet connectivity with Silicon-Proven 224G SerDes IP on TSMC’s 3nm Process

Ethernet design starts are normally ahead of the IEEE & OIF specification release. The 1.6T Ethernet standard is no exception. Companies are already designing SoCs for a wide range of applications requiring 1.6T SerDes. This presentation delves into the critical role of 112G/224G SerDes technology for 800G and 1.6T Ethernet applications. We will examine the implementation and benefits of PAM-4 signaling and robust Forward Error Correction (FEC) algorithms for enhancing link reliability and maintaining signal integrity at the fastest data transmission speeds. Learn how to confidently transition to terabit-scale Ethernet connectivity utilizing silicon proof of the Synopsys 224G and 112G Ethernet PHY IP on TSMC’s 3nm process.

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