 |
| HPC & 3DFabric Track |
 |
Enabling the transition to terabit-scale Ethernet connectivity with Silicon-Proven 224G SerDes IP on TSMC’s 3nm Process
Synopsys
|
 |
Abstract
Ethernet design starts are normally ahead of the IEEE & OIF specification release. The 1.6T Ethernet standard is no exception. Companies are already designing SoCs for a wide range of applications requiring 1.6T SerDes. This presentation delves into the critical role of 112G/224G SerDes technology for 800G and 1.6T Ethernet applications. We will examine the implementation and benefits of PAM-4 signaling and robust Forward Error Correction (FEC) algorithms for enhancing link reliability and maintaining signal integrity at the fastest data transmission speeds. Learn how to confidently transition to terabit-scale Ethernet connectivity utilizing silicon proof of the Synopsys 224G and 112G Ethernet PHY IP on TSMC’s 3nm process. |
|
Legal Notice
TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC. |
|
