IoT, RF & Other Track   13:00 – 13:30

Synopsys AI-based Analog Design Migration Flow for TSMC Advanced Technologies

With the ever-growing demand for high performance SOC, leveraging the most advanced technology nodes such as TSMC N4P, N3 and N2, and with demanding time-to-market constraints and limited engineering resources, design teams are looking for innovative way to best reuse previous designs that were designed on “older” nodes, and be able to migrate those design from node to node.

Analog design in advanced technology nodes is particularly challenging to optimize duo to the need to account for layout effects (LDE and RC) in the design centering and optimization process. These LDE and RC effect are often time a 1st-order effect on circuit performance, and the old “chicken and egg” challenge of, the need to have a layout, in-order to extract parasitic to be included in simulation and optimization of the design and then… re-do the layout again… and again… and again.

Custom Compiler AI-based design migration and optimization solution is being developed to solve that challenge by introducing a novel technique that enable concurrent optimization of both schematic and layout, where the optimizer can optimize design parameter in schematics and automatically update the layout.

In this presentation we will review the flow and solution being developed and show results of a complete designs optimization done on TSMC most advanced technology nodes.

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