HPC & 3DFabric Track   11:00 – 11:30

A Case Study Demonstrating the Advantages of 224G Interconnects and 3DIC Architectures for Artificial Intelligence ICs

Alchip / Synopsys
Abstract
The need for increased computational power to handle complex neural networks and large datasets is one of the major challenges for artificial intelligence (AI) chip design. Traditional architectures struggle to efficiently meet these requirements. However, 224G SerDes technology enables larger scale 2D and 3D interconnection that consumes less power, in a smaller footprint and with greater efficiency.
In addition, 3DIC integration allows larger, more complex neural networks to be stored and processed directly on one chiplet, reducing the need for frequent data transfers to external memory. This improvement enhances computational efficiency, reduces energy consumption, and enables real-time processing of larger datasets. The 3DIC technology stacks compute dies on top of memory and interconnect dies using high-density through-silicon-vias (TSV) and hyper bumps, resulting in an increased compute transistor density, larger SRAM die, shorter interconnects, and improved power efficiency with minimal latency.
The combination of 224G interconnects and 3DIC chiplets offers significant advantages in modern AI chip design, addressing the challenges of computational power, memory capacity, and interconnect optimization. Engineers can leverage these advancements to push the boundaries of AI capabilities, leading to more powerful, efficient, and scalable artificial intelligence systems.
This presentation, by Alchip and Synopsys, examines how the challenge for increased computational power in AI chips can be addressed by leveraging 224G interconnects and 3DIC architectures. The presentation details the companies’ collaboration and shares the results.
Alchip utilized its Chiptopia design platform, a proven framework, its proven design flow and methodology, and the Synopsys 3DIC Compiler to create a unified platform for die/package exploration, co-design, and analysis. The platform also assembles the bottom die, top die, interconnects, and thermal solutions.
Alchip designed a 3DIC chip using TSMC’s CoWoS advanced packaging to integrate the 224G SerDes, leveraging Synopsys 224G SerDes IP. The package design has undergone thorough simulation for signal integrity (SI), power integrity (PI), and thermal considerations. The systems house partner provided guidance on package breakout, thermal management, and PI considerations. Subsequently, they successfully completed a comprehensive system design.

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