| Time |
Plenary Session |
| 08:00 - 09:00 |
Registration & Ecosystem Pavilion |
| 09:00 - 09:15 |
Welcome Remarks |
| 09:15 - 10:10 |
TSMC Keynote & Guest Speech |
| 10:10 – 10:30 |
Coffee Break & Ecosystem Pavilion |
| 10:30 – 11:00 |
TSMC 3Dblox™ Talk |
TSMC 3DFabric™ Talk |
TSMC Analog Migration Talk |
|
HPC & 3DFabric Track |
Mobile & Automotive Track |
IoT, RF & Other Track |
| 11:00 – 11:30 |
A Case Study Demonstrating the Advantages of 224G Interconnects and 3DIC Architectures for Artificial Intelligence ICs
Alchip
/ Synopsys
|
Gaining PPA (3.4+GHz) & Productivity advantage on TSMC N3E Implementation of Arm Cortex-X4 and Next-Gen CPUs using Cadence Solutions
Cadence
/ ARM
|
Synopsys/Ansys/Keysight RF Reference Design Flow on TSMC Advanced N4P Process
Synopsys
/ Keysight / Ansys
|
| 11:30 – 12:00 |
Accelerating stacked-die design with 3D Design platform using TSMC 3Dblox and Cadence’s Integrity 3D-IC Platform
Cadence
/ Socionext
|
Demonstrating Technology PPA Entitlement with TSMC’s N2 Technology on HPC Design Using Synopsys Fusion Compiler
Synopsys
|
High Voltage (>10V) RF and Analog Interfaces for Standard Low Voltage CMOS TSMC Processes
Siemens EDA
/ Certus Semiconductor
|
| 12:00 – 13:00 |
Lunch & Ecosystem Pavilion |
| 13:00 – 13:30 |
3DIC test challenges and DFT development experience with Tessent Multi-die
Siemens EDA
/ Broadcom
|
Achieving TSMC N3 and N2 design goals using Cadence Cerebrus AI enabled digital full flow
Cadence
|
Synopsys AI-based Analog Design Migration Flow for TSMC Advanced Technologies
Synopsys
|
| 13:30 – 14:00 |
Using 3Dblox™ to simplify and automate 3DFabric design
Cadence
|
Unlocking the Power of Data: Enabling a Safer Future for Automotive Systems
proteanTecs
|
Driving AIoT Innovation: M31 N12e low power IP
M31 Technology
|
| 14:00 – 14:30 |
The Next Wave: 224G Serial Link
Cadence
|
Maximize Designer Productivity with AI-Driven EDA Vertical Stack
Synopsys
|
Custom Design Migration in Virtuoso Studio: A comprehensive solution for migration across nodes
Cadence
|
| 14:30 – 15:00 |
3DIC Multiphysics Simulation Technologies Enabled by Ansys RedHawk-SC, RedHawk-SC Electrothermal and TSMC 3Dblox
ANSYS
|
Optimizing compute density for SiFive RISC-V processors in TSMC advanced nodes with Synopsys Fusion QuickStart Implementation Kits
Synopsys
/ SiFive
|
A methodology for PDK migration and validation integrated in Virtuoso Studio
Cadence
|
| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 16:00 |
GUC’s Chiplet Solutions from 2.5D to 3D
GUC
|
Addressing reliability challenges with aging-aware STA for advanced nodes
Cadence
/ nVidia
|
Cisco Characterization using PrimeLib on Synopsys Cloud for TSMC Advanced Node Libraries
Synopsys
/ Cisco
|
| 16:00 – 16:30 |
The Rise of Chiplets in Advanced AI / ML / High Performance Compute SoC's
Credo Semiconductor
|
Achieving Ultra Low Power Designs on TSMC Advanced Nodes using Synopsys Foundation IP
Synopsys
|
Using Generative AI to accelerate silicon design
Microsoft
|
| 16:30 – 17:00 |
Enabling Realistic Disaggregated System through UCIe Interconnect and Chiplets-based design.
Alphawave Semi
|
Attacking resistance, the key limiter in achieving EMIR clean results, with layout modifications
Siemens EDA
/ MediaTek
|
Leveraging UCIe for High-Speed Stack Testing of Multi-Die Systems through Monitoring, Test & Repair (MTR) and HSAT IPs
Synopsys
/ TSMC
|
| 17:00 – 17:30 |
Real Examples of 3D Heterogeneous Integration Using the TSMC 3Dblox Standard
Synopsys
|
AWS and Siemens EDA Collaborate to Accelerate Your Migration to the Cloud
Siemens
/ Amazon Web Services (AWS Cloud)
|
Virtual cross-die Coupling Capacitance Extraction Using Synopsys StarRC
Synopsys
|
