|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:40 |
Welcome Remarks |
| 09:40 - 10:40 |
TSMC Keynote & Guest Speech |
| 10:40 – 11:00 |
Coffee Break & Ecosystem Pavilion |
| 11:00 – 11:30 |
TSMC 3Dblox™ Talk
TSMC
|
TSMC 3DFabric™ Talk
TSMC
|
TSMC Analog Migration Talk
TSMC
|
|
HPC & 3DFabric Track |
Mobile & Automotive Track |
IoT, RF & Other Track |
| 11:30 – 12:00 |
A Case Study Demonstrating the Advantages of 224G Interconnects and 3DIC Architectures for Artificial Intelligence ICs
Alchip
/ Synopsys
|
Gaining PPA (3.4+GHz) & Productivity advantage on TSMC N3E Implementation of Arm Cortex-X4 and Next-Gen CPUs using Cadence Solutions
Cadence
/ ARM
|
Synopsys/Ansys/Keysight RF Reference Design Flow on TSMC Advanced N4P Process
Synopsys
/ Keysight / Ansys
|
| 12:00 - 12:30 |
Addressing reliability challenges with aging-aware STA for advanced nodes
Cadence
/ nVidia
|
Demonstrating Technology PPA Entitlement with TSMC’s N2 Technology on HPC Design Using Synopsys Fusion Compiler
Synopsys
|
mm-wave Communication Circuits in 16nm FinFET
KU Leuven
|
| 12:30 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 14:00 |
GUC’s Chiplet Solutions from 2.5D to 3D
GUC
|
Achieving TSMC N3 and N2 design goals using Cadence Cerebrus AI enabled digital full flow
Cadence
|
Synopsys AI-based Analog Design Migration Flow for TSMC Advanced Technologies
Synopsys
|
| 14:00 – 14:30 |
Using 3Dblox to simplify and automate 3DFabric design
Cadence
|
Unlocking the Power of Data: Enabling a Safer Future for Automotive Systems
proteanTecs
|
Novel Computing Paradigm based on Oscillatory Neural Networks for Energy Efficient Edge AI
Eindhoven University of Technology
|
| 14:30 – 15:00 |
Real Examples of 3D Heterogeneous Integration Using the TSMC 3Dblox Standard
Synopsys
|
New Approach to lower Jitter in a PLL
Technical University of Munich
|
A methodology for PDK migration and validation integrated in Virtuoso Studio
Cadence
|
| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 16:00 |
The Rise of Chiplets in Advanced AI / ML / High Performance Compute SoC's
Credo Semiconductor
|
Optimizing compute density for SiFive RISC-V processors in TSMC advanced nodes with Synopsys Fusion QuickStart Implementation Kits
Synopsys
/ SiFive
|
Cisco Characterization using PrimeLib on Synopsys Cloud for TSMC Advanced Node Libraries
Synopsys
/ Cisco
|
| 16:00 – 16:30 |
Enabling Realistic Disaggregated System through UCIe Interconnect and Chiplets-based design.
Alphawave Semi
|
On-Die Power Management IP's for SoCs and Chiplets on N3P Process
Analog Bits
|
Attacking resistance, the key limiter in achieving EMIR clean results, with layout modifications
Siemens EDA
/ MediaTek
|
| 16:30 – 17:00 |
Massive Parallel Oscillator Networks to Solve NP-hard Combinatorial Optimization Problems
TU Darmstadt
|
Enabling the automotive chiplet ecosystem
Imec
|
Custom Design Migration in Virtuoso Studio: A comprehensive solution for migration across nodes
Cadence
|
| 17:00 – 17:30 |
Synopsys SLM PVT Monitor IP readiness on TSMC N3E/N3P/N3AE
Synopsys
|
Analog Computing based on Oscillatory Neural Networks for Solving Combinatorial Optimization Problems.
LIRMM
|
Ultra low power analog front ends and digitizers
Eindhoven University of Technology
|
| 17:30 - 18:30 |
Networking and Reception |
