|
Time
|
Plenary Session
|
| 08:30 - 09:30 |
Registration & Ecosystem Pavilion |
| 09:30 - 09:45 |
Welcome Remarks |
| 09:45 - 10:30 |
TSMC Keynote |
| 10:30 – 11:00 |
Coffee Break & Ecosystem Pavilion |
| 11:00 – 11:30 |
TSMC 3Dblox & 3DFabric Flow
TSMC
|
TSMC Analog Migration
TSMC
|
|
HPC & 3DIC Track |
Mobile, IoT & Automotive Track |
| 11:30 – 12:00 |
An Accurate Multiphysics Thermal Solution for Large Scale 3DIC Design
Sanechips
/ Ansys
|
Optimizing compute density for SiFive RISC-V processors in TSMC advanced nodes with Synopsys Fusion QuickStart Implementation Kits
Synopsys
/ SiFive
|
| 12:00 - 12:30 |
A Case Study Demonstrating the Advantages of 224G Interconnects and 3DIC Architectures for Artificial Intelligence ICs
Alchip
/ Synopsys
|
A Novel methodology for GPGPU power delivery network design to improve the power and performance
Iluvatar CoreX
/ Ansys
|
| 12:30 – 13:30 |
Lunch & Ecosystem Pavilion |
| 13:30 – 14:00 |
Application of SI Pre-Simulation Technology in Advanced Package Technology
Sanechips
|
Cisco Characterization using PrimeLib on Synopsys Cloud for TSMC Advanced Node Libraries
Synopsys
/ Cisco
|
| 14:00 – 14:30 |
GUC’s Chiplet Solutions from 2.5D to 3D
GUC
|
Attacking resistance, the key limiter in achieving EMIR clean results, with layout modifications
Siemens EDA
/ MediaTek
|
| 14:30 – 15:00 |
The Rise of Chiplets in Advanced AI / ML / High Performance Compute SoC's
Credo Semiconductor
|
The SoC Anchor in Advanced Technology: An One-stop-shop NeoFuse NVM Solution
eMemory Technology Inc.
|
| 15:00 – 15:30 |
Coffee Break & Ecosystem Pavilion |
| 15:30 – 16:00 |
Leveraging UCIe for High-Speed Stack Testing of Multi-Die Systems through Monitoring, Test & Repair (MTR) and HSAT IPs
Synopsys
/ TSMC
|
Using a safety-intent driven digital implementation flow for advanced node automotive applications
Cadence
/ Sanechips
|
| 16:00 – 16:30 |
Using 3Dblox to simplify and automate 3DFabric design
Cadence
|
Driving AIoT Innovation: M31 N12e low power IP
M31 Technology
|
| 16:30 – 17:00 |
Real Examples of 3D Heterogeneous Integration Using the TSMC 3Dblox Standard
Synopsys
|
Improve SRAM characterization LVF flow performance with Cadence Liberate MX Trio and Spectre FMC Analysis Integration
Cadence
|
| 17:00 – 17:30 |
Holistic IR: Improving System Stability and Yield by Mastering Power Delivery at both IC and System Levels
紫光展锐
|
safety-aware implementation
Semidrive
/ Candence
|
| 17:30 - 17:45 |
Lucky Draw |
