ONLINE

North America

August 24-25, 2020

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Overview
Registration

Technology Symposium

Aug. 24th

Speakers

C.C. Wei, CEO

Industry Overview and Corporate Updates

C.C. Wei, CEO

Y.J. Mii, SVP, R&D

Advanced Technology Leadership

Y.J. Mii, SVP, R&D

Kevin Zhang, VP, BD

Specialty Technology Leadership

Kevin Zhang, VP, BD

Doug Yu, VP, R&D

Advanced Packaging Technology Leadership

Doug Yu, VP, R&D

Y.P. Chin, SVP, Operations

Manufacturing Excellence

Y.P. Chin, SVP, Operations

Open Innovation Platform®
Ecosystem Forum

Aug. 25th

Speakers

Cliff Hou, SVP, R&D

TSMC Ecosystem for Innovation

Cliff Hou, SVP, R&D

Lip-Bu Tan, CEO Cadence

Partner Feature Talk

Lip-Bu Tan, CEO, Cadence

Dr. Aart de Geus, CEO Synopsys

Partner Feature Talk

Aart de Geus, CEO, Synopsys

Joseph Sawicki, Executive VP Mentor

Partner Feature Talk

Joseph Sawicki, EVP, Mentor

Track Sessions

HPC & 3DIC
Mobile & Automotive
IoT & RF
【
Best Practices Designing Ultra Large-scale Machine Learning ASIC

Alchip

The Path to 200Gbps Serial Links

AlphaWave

Case Study of AI Wafer Scale SoC from Cerebras Systems using Analog Bits Power Integrity Sensors

Analog Bits / Cerebras

Design and Verification of 7nm FF PCIe Gen5 Clock Subsystem with Multi-Protocol Programmability

Analog Bits

RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Arrays

Andes

Comprehensive Thermal Solution from Architecture to Layout for Large SoC and 3DIC

Ansys

Not All 112G/56G SerDes Are Born Equal—Select the Right PAM4 SerDes for Your Application

Cadence

Optimized Digital Design, Implementation, and Signoff on TSMC’s N3

Cadence

TSMC Timing Signoff in the Cloud with Cadence Tempus and Quantus Solutions

Cadence

Using Timing Robustness as a Metric to Optimize Design PPA

Cadence

Enabling AI/ML, HPC & Networking Products Using TSMC 2.5D/3D Advanced Packaging Technology with GUC's Interface IPs

GUC

MIPI C/D-PHY TX and RX IP for Sensor Application

M31

Circuit Design and Verification of 5nm and 3nm Programmable PLLs for HPC,Mobile, Automotive, and IoT Applications

Mentor / Silicon Creations

Fast-track your early SoC design exploration and verification

Mentor

Challenges of N5 HPC Hyper-scaling within Data Centres

Moortec

Memory Systems for AI Applications Using TSMC Advanced Process Nodes

Rambus

Versatile, wide range 12FFC/16FFC SerDes 250Mbps to 16Gbps SerDes PMA meeting challenging standards and applications

Silicon Creations

Reliable Die-to-Die Interfaces for High-Performance Computing SoCs on TSMC's FinFET Processes

Synopsys

Scaling Physical Verification Workloads on the Cloud

Synopsys / AMD / Microsoft

Specialty Foundation IP for AI/ML SoCs on TSMC's 7nm and 5nm Processes

Synopsys

AWS Cloud for Secure IP Collaboration – Lessons Learned at Amazon

Amazon

Delivering a Low-Power Arm Hercules Mobile 7nm CPU Using the Cadence Digital Flow

Cadence

Updating Your Automotive SoC from 16FFC to N7—Process, Design, Reliability, and Functional Safety Considerations

Cadence

Accelerating Design at TSMC’s N5 Process Technology Node using Fusion Compiler and the wider Synopsys Digital Design Platform

Synopsys

Case Study: Design-in-the-Cloud: Myth and Reality

Synopsys / ST

Enabling USB4 40 Gbps Designs on TSMC N5 & N6 Processes with DesignWare USB4 IP

Synopsys

Electromigration and Self Heat analysis on RF devices for mmWave designs

Ansys

A Painless Upgrade to 22nm for Ultra-low Power Designs

Arm / Ambiq Micro

Airoha’s Optimal Bluetooth Audio SoC design using Arm Artisan library on TSMC 22ULL technology

Arm / Airoha

Using TSMC Analog Cells for Improving Design Productivity

Cadence

Innovative Ultra-Low-Power Voice recognition solutions powered by Dolphin SPEED Platforms in TSMC 22ULL

Dolphin Design

Comprehensive OTP and secure solutions in tsmc 22/16/12nm platforms for IoT applications

eMemory

M31 Comprehensive Physical IP Portfolio on 22nm Platform

M31

Calibre PERC: New Techniques for Leakage Verification

Mentor

Selecting the right ESD robustness level for IoT applications – Overview of different application examples

Sofics

Transforming Multi-Die Integration with InFO Wafer Level Packaging

Synopsys